Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device
US5493531A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1994 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Dec 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for checking the utilization rate of redundancy memory elements in semiconductor memory device, comprising a matrix of memory elements and a redundancy circuitry which comprises a plurality of programmable non-volatile memory registers, each supplied with address signals to generate a redundancy selection signal for the selection of an associated redundancy memory element when the address signals coincide with the address stored therein, and combinatorial circuit means supplying the non-volatile memory registers with an inhibition signal for inhibiting the generation of the respective redundancy selection signals when the address signals coincide with the address stored in a non-programmed non-volatile memory register; the integrated circuitry comprises multiplexing circuit means, controlled by a control signal generated by a control circuitry of the memory device, for transmitting the redundancy selection signals to output pads of the memory device when the control signal is activated; the control signal is also supplied to said combinatorial circuit means to prevent when activated the generation of said inhibition signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.