Method improving integrated circuit planarization during etchback

US5496774A · kind A · utility

Assignee

• VLSI Technology, Inc. · US

Inventors

• Dipankar Pramanik · Saratoga, US
• Vivek Jain · Sammamish, US
• Milind Weling · San Jose, US

Key dates

• Filing date: Dec 21, 1994
• Grant date: Mar 5, 1996
• Expiry date: Dec 21, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76819
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto. A second metal layer is deposited on the oxide layer and the fabrication process continues until the integrated circuit is complete.