Semiconductor processing methods of forming stacked capacitors
US5498562A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1994 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Apr 29, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
In one aspect of the invention, an insulative nitride oxidation barrier layer is provided over a cell polysilicon layer to a thickness of at least about 150 Angstroms. An insulating layer is provided above the nitride oxidation barrier layer, and an contact/container is etched therethrough and through dielectric and cell polysilicon layers. Such exposes edges of the cell polysilicon within the contact/container. The wafer is then exposed to an oxidizing ambient to oxidize the cell polysilicon exposed edges, with the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer. In another aspect, a multi-container stacked capacitor construction has its containers defined or otherwise electrically isolated in a single CMP step. In another aspect, a combination etch stop/oxidation barrier layer or region is provided to enable exposure of a precise quantity of the outside walls of a stacked capacitor container.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.