Bias circuit for a memory line decoder driver of nonvolatile memories
US5499217A · kind A · utility
5Cited by
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23Claims
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Key dates
| Filing date | Dec 2, 1994 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Dec 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage alternatively connects the gate terminal of the pull-up transistor to a capacitor, with which the charge is distributed, and to the supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.