Data processor with speculative data transfer and address-free retry
US5500950A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1993 |
| Grant date | Mar 19, 1996 |
| Priority date | — |
| Expiry date | Jan 29, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor with speculative data transfer has address circuitry (40) and data circuitry (42, 44). The address circuitry generates a memory address associated with a data block and with a tag. The tag is representative of the validity of the data block. The data circuitry receives the data block associated with the memory address at a first time and receives a signal at a second subsequent time. The signal is representative of the validity of the data block. The data circuitry rejects the data block responsive to the signal. The data processor is able to receive data while the validity of the data is determined in parallel by, for instance, an address comparison or an error correcting code scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.