Method for planarizing an integrated circuit topography
US5503882A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 1994 |
| Grant date | Apr 2, 1996 |
| Priority date | — |
| Expiry date | Apr 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31051
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a planarization structure of dielectric materials upon a substrate topography. The dielectric materials can be deposited in layers without removing one or more layers in non-contact areas prior to deposition of an overlying interconnect conductors. Alternatively, at least one layer can be entirely removed from the dielectric materials prior to deposition of the overlying interconnect conductors. A plasma oxide is placed between the substrate upper surface and a subsequently deposited TEOS oxide to reduce stress properties and to balance the stress between the TEOS oxide and the plasma oxide. A subsequently placed SOG layer can be used to further planarize the upper surface, wherein a capping layer is deposited above the SOG to prevent or substantially minimize water absorption. The SOG layer can, alternatively, be removed in its entirety in an etch-back procedure prior to capping layer deposition. Removal of the SOG layer prevents outgassing of water during times in which contacts are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.