CMOS locos isolation for self-aligned NPN BJT in a BiCMOS process
US5504364A · kind A · utility
16Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1994 |
| Grant date | Apr 2, 1996 |
| Priority date | — |
| Expiry date | Aug 24, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.