Low temperature process for fabricating layered superlattice materialsand making electronic devices including same
US5508226A · kind A · utility
33Cited by
4References
30Claims
0Family size
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Key dates
| Filing date | Mar 21, 1995 |
| Grant date | Apr 16, 1996 |
| Priority date | — |
| Expiry date | Mar 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A liquid precursor containing a metal is applied to a first electrode, RTP baked at a temperature of 700.degree. C., and annealed at the same temperature for from 3 to 5 hours to form a layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature of 700.degree. C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8.ltoreq.u.ltoreq.1.0, 2.0 v.ltoreq.2.3, and 1.9.ltoreq.w.ltoreq.2.1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.