LDMOS transistor with reduced projective area of source region
US5508547A · kind A · utility
7Cited by
2References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 18, 1994 |
| Grant date | Apr 16, 1996 |
| Priority date | — |
| Expiry date | Oct 18, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/168
Abstract
Reduced-size LDMOS transistor having reduced leakage and a reduced propensity to latch-up. The LDMOS transistor has a trench with vertical sidewalls adjacent to a source region to help reduce a vertical projective area of the source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.