Polishstop planarization structure
US5510652A · kind A · utility
46Cited by
27References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1994 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Oct 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a method for producing a substantially planar surface overlying features of a semiconductor structure. The method comprises forming alternating layers of a hard polishing material and a soft polishing material over the features of the semiconductor structure, and then polishing the alternating layers to form a substantially planar surface over the features. The method takes advantage of the polish rates of the various materials used as alternating layers to enhance the planarization process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.