Dynamic random access memory system
US5511024A · kind A · utility
96Cited by
16References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1994 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Feb 25, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.