Write per bit with write mask information carried on the data path past the input data latch
US5511025A · kind A · utility
26Cited by
5References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 21, 1994 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Dec 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.