Method of making lightly-doped drain DMOS with improved breakdown characteristics
US5514608A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1994 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Oct 4, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
Abstract
An LDD lateral DMOS transistor is provided in a lightly-doped epitaxial layer of a first conductivity above a substrate of the same conductivity. A highly-doped buried layer of the first conductivity is provided under the LDD lateral DMOS transistor to relieve crowding of electrical equipotential distribution beneath the silicon surface. In one embodiment, a gate plate is provided above the gate and the gate-edge of the drift region. An optional N-well provides further flexibility to shape electric fields beneath the silicon surface. The buried layer can also reduce the electric field in a LDD lateral diode and improves cathode-to-anode reversed-recovery characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.