Method of making layout design to eliminate process antenna effect
US5514623A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1995 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Feb 13, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/91
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-level conductive interconnection for an integrated circuit is formed in a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. A patterned layer of a polysilicon layer is formed on the substrate to act as a first contact to the integrated circuit. An insulating layer is formed over the polysilicon layer, and openings to the polysilicon layer are formed through the insulating layer. A first layer of metal is formed on the insulator such that the metal electrically connects to the polysilicon through the openings, and also forms large contact pad areas. The first metal is patterned to form an electrical break between the large contact pad areas and the integrated circuit. This break prevents electrical damage to the integrated circuit due to charge build-up during subsequent processing in a plasma environment. A second insulating layer is formed and patterned to provide openings for vias to the first metal layer. A second layer of metal is formed over the large contact pad area and over the electrical break such that the second metal electrically connects to the first metal, by direct contact to the first metal at the large con…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.