Very high density wafer scale device architecture
US5514884A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 1994 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | May 23, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements. As another novel feature, the structure may include two or more address ports, which may simultaneously address different banks of the repeating elements. The plural address port feature is particularly useful for automatic refreshing of dynamic random access memories (…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.