Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate
US5516729A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1994 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Jun 3, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/959
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a planarization structure of dielectrical materials upon a substrate topography. The dielectric materials are deposited as first and second insulating layers. The second, and then the first insulating layers are partially removed by chemical-mechanical polish (CMP). Prior to CMP, the second insulating layer of variable chemical and mechanical properties can be fixed at a preferred chemical or mechanical characteristic which makes it more or less susceptible to subsequent CMP. Accordingly, the present invention utilizes a second insulating layer of adjustable properties necessary to more adequately planarize during application of CMP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.