Process for fabricating a CMOS transistor having high-voltage metal-gate

US5518938A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventor

• Sheng-Hsing Yang · Hsinchu, TW

Key dates

• Filing date: May 8, 1995
• Grant date: May 21, 1996
• Expiry date: May 8, 2015

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/082

Abstract

A process for fabricating a high-voltage metal-gate CMOS transistor is disclosed. The CMOS transistor comprises a pair of complementary NMOS and PMOS transistors. The CMOS transistor is fabricated on an semiconductor substrate of a first conductivity type, which has a well region of a second conductivity type therein; therefore, the PMOS and NMOS are fabricated onto the substrate or well region, separately. It can be understood that use of the opening prepared in the initial, and, the only primary shielding layer for the location of the source/drain regions of both the NMOS and PMOS transistors, comprises the key to the precision alignment, and to the dimensional symmetry of the transistors fabricated. This is because that the subsequent fabrication procedural steps after the formation of the shielding layer with the set openings, including all the deposition, the ion implantation, and the etching, etc., all utilize the single positioned reference as set up in the initial shielding layer, with its initial openings defining the locations of the source/drain, as well as the gate regions for the transistors. This allows to ensure the uniformity of the electrical characteristics of the…