Method of fabricating a high-voltage metal-gate CMOS device
US5523246A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 1995 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Jun 14, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/082
Abstract
A method of fabricating a high-voltage metal-gate CMOS device is disclosed. First, a semiconductor substrate of a first conductivity type having a well region of a second conductivity type is provided. Next, a barrier layer is formed and patterned to form openings for prospective source/drain regions. Then, through the openings, low concentrations of impurities of the first conductivity type and the second conductivity type are implanted into the well region and the semiconductor substrate, respectively. After performing a first thermal treatment, lightly doped source/drain regions of the first conductivity type and the second conductivity type are formed respectively, wherein an oxide layer is also formed within the openings. A sidewall spacer is formed on the sidewalls of the openings. Then, through the openings, high concentrations of impurities of the first conductivity type and the second conductivity type are implanted into the lightly doped source/drain regions of the first conductivity type and the second conductivity type, respectively. After removing the sidewall spacer performing a second thermal treatment, heavily doped source/drain regions of the first conductivity typ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.