Cache system and method for providing software controlled writeback
US5524225A · kind A · utility
35Cited by
4References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1992 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Dec 18, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and mechanism for controlling the data transfers between a system memory and a cache memory is provided. The mechanism includes a cache controller with a physical address register coupled to a bus. Software may alter the operation of the cache controller to force blocks in the cache memory to be written back to the system memory by sending control signals to the physical address register over the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.