Flash EPROM integrated circuit architecture
US5526307A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1994 |
| Grant date | Jun 11, 1996 |
| Priority date | — |
| Expiry date | Oct 26, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes a memory array having at least M rows and 2N columns of flash EPROM cells. M word lines, each coupled to the flash EPROM cells in one of the M rows of the flash EPROM cells, and N global bit lines are included. Data in and out circuitry is coupled to the N global bit lines which provide for reading and writing data in the memory array. Selector circuitry, coupled to the 2N columns of flash EPROM cells, and to the N global bit lines, provides for selective connection of two columns of the 2N columns to each of the N global bit lines so that access to the 2N columns of flash EPROM cells by the data in and out circuitry is provided across N global bit lines. The semiconductor substrate has a first conductivity type, a first well in the substrate of a second conductivity type, and a second well of the first conductivity type in the first well. The flash EPROM cells are made in the second we…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.