Thin film chip capacitor for electrical noise reduction in integrated circuits
US5528083A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1994 |
| Grant date | Jun 18, 1996 |
| Priority date | — |
| Expiry date | Oct 4, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/924
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip and flat capacitor assembly are connected with short bonding wires to reduce electrical noise. A flat chip capacitor is coupled to the chip and includes a first electrode, a second electrode and a dielectric layer disposed between the electrodes. The ground and power bonding pads of an integrated circuit chip are coupled to a number of terminals arranged in a row near the outer edge of the capacitor, where each of the terminals is coupled to one of the electrodes. The terminals of the capacitor are connected to a number of package leads of a lead frame or a other integrated circuit package. The invention includes embodiments in which the chip is placed on top of the capacitor, the capacitor is placed on top of the chip, and a flex circuit of a micro ball grid array is placed on a capacitor which is positioned on a chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.