High speed global row redundancy system
US5528539A · kind A · utility
100Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1994 |
| Grant date | Jun 18, 1996 |
| Priority date | — |
| Expiry date | Sep 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.