Direct stacked and flip chip power semiconductor device structures
US5532512A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1994 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | Oct 3, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Power semiconductor device structures and assemblies with improved heat dissipation characteristics and low impedance interconnections include a thermally-conductive dielectric layer, such as diamondlike carbon (DLC) overlying at least portions of the active major surface of a semiconductor chip, with vias formed in the dielectric layer in alignment with contact pads on the active major surface. A patterned metallization layer is formed over the thermally-conductive dielectric layer, with portions of the metallization layer extending through the vias into electrical contact with the chip contact pads. A metal structure is electrically and thermally coupled to selected areas of the patterned metallization, such as by solder bonding or by a eutectic bonding process. In different embodiments, the metal structure may comprise a metal conductor bonded to the opposite major surface of another power semiconductor device structure, a heat-dissipating device-mounting structure, or simply a low-impedance lead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.