Method and circuit for timing the reading of nonvolatile memories
US5532972A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1995 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | Feb 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.