Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry

US5534449A · kind A · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Charles H. Dennison · San Jose, US
• Mark A. Helm · Boise, US

Key dates

• Filing date: Jul 17, 1995
• Grant date: Jul 9, 1996
• Expiry date: Jul 17, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856

Abstract

A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and th…