Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5537580A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1994 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Dec 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an integrated circuit includes the steps of: (a) describing the functionality of an integrated circuit in terms of a behavioral hardware description language, where the hardware description language describes behavior which can be extracted as a state machine; (b) extracting a register level state machine transition table of the state machine from the hardware description language; (c) generating a logic level state transition table representing the state machine from the register level state machine description; (d) creating a state machine structural netlist representing the state machine from the logic level state transition table; and (e) combining the state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist including the state machine to provide a basis for chip compilation, mask layout and integrated circuit fabrication. The method results in a synchronous state machine being extracted from an register-transfer (RT) level representation taken from a scheduled behavioral hardware description language description such as a Verilog or VHDL. Behavioral hardware description lan…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.