Device and method for reducing bus activity in a computer system having multiple bus-masters
US5546560A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 1993 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | Jun 22, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and device for avoiding unnecessary data broadcasts by detecting the presence of additional cache-equipped bus-masters is provided. The device includes a master bus-master equipped with a local cache arrangement for caching data originating in a system memory. The master bus-master communicates with the system memory over a bus, and is coupled to a control line at an input. Any cache-equipped slave bus masters that are caching data with the system memory are coupled to the control line by an output and are configured to generate a signal at the output to drive the control line to a predetermined state to indicate that they are caching data. The master bus-master detects the state of the control line and determines whether the data being buffered in its local cache arrangement is shared based upon the state of the control line. If the state of the control line indicates the presence of other cache-equipped bus-masters, the master bus-master automatically broadcasts data that it modifies; otherwise it writes the modified data back to the system memory when the cache space occupied by the modified data is required for new data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.