Method of fabricating a metal gate MOS transistor with self-aligned first conductivity type source and drain regions and second conductivity type contact regions
US5547895A · kind A · utility
8Cited by
7References
16Claims
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Key dates
| Filing date | Aug 31, 1994 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Aug 31, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method for manufacturing a CMOS transistor of integrated circuits having metal gates and self-aligned source and drain electrodes. The channel length can be precisely defined, and the leakage current can be reduced. Furthermore, the threshold voltage of the transistor can be increased by implanting impurities into the well or the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.