Integrated programming circuitry for an electrically programmable semiconductor memory device with redundancy
US5548554A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1994 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Dec 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits, each one associated with a respective memory matrix portion or group of columns, and a plurality of programming load control circuits, each one controlling the activation of one respective programming load circuit according to the logic state of a respective data line carrying a datum to be programmed; the memory device comprises a group of redundancy bit lines and an associated redundancy programming load circuit; each programming load control circuit comprises decoding means supplied with signals which, when a defective column address is supplied to the memory device during programming, are generated from a matrix portion identifying code stored in a non-volatile register wherein the defective column address is stored, and switch means responsive to a decoded signal at the output of said decoding means to enable the activation of the redundancy programming load circuit according to the logic state of the data signal line and to cause the inhibition of the activation of the respective programming load circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.