Process for fabricating MOS transistors having anti-punchthrough implant regions formed by the use of a phase-shift mask
US5550074A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1996 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Jan 19, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/948
Abstract
Disclosed is a semiconductor fabrication process for fabricating MOS transistors in which ions are implanted only beneath the channel and are not overlapped with the source/drain regions so as to significantly reduce the junction capacitance of the source/drain regions for performance enhancement. The process comprises a first step of preparing a silicon substrate on which a field oxide region is formed to define an active region. In the second step, a phase-shift mask is used to define a substantially rectangular removal portion on a photoresist layer. One side of the rectangular removal portion is substantially aligned with the channel of the MOS transistor to be fabricated and the other three sides are placed within the field oxide region. In the third step, an anti-punchthrough implantation process is performed, in which ions are implanted through the removal portion of the photoresist layer to form an anti-punchthrough implant region beneath the channel of the MOS transistor; and in the final step, a gate region and source/drain regions are formed. The thus formed anti-punchthrough implant region is right beneath the channel of the MOS transistor and does not overlap with the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.