Method of fabricating electrically eraseable read only memory cell having a trench
US5554550A · kind A · utility
32Cited by
4References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 14, 1994 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Sep 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
A method of fabricating an EPROM cell by forming a trench in a semiconductor substrate, forming a first insulating layer over the surface of the substrate, and the sidewalls and bottom of the trench, forming individual polycrystalline silicon layers on the sidewalls of the trench, implanting a dopant into the substrate in the bottom of, and regions adjacent, the trench, forming a second insulating layer over the polycrystalline silicon layers, forming a control gate over the polycrystalline silicon layers and an electrical contact to the bottom of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.