Connection and build-up technique for multichip modules

US5556812A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Rainer Leuschner · Regensburg, DE
• Hellmut Ahne · Königsee, DE
• Siegfried Birkle · Höchstadt an der Aisch, DE
• Albert Hammerschmidt · Erlangen, DE
• Recai Sezi · Simmerath, DE
• Tobias Noll · Neckartailfingen, DE
• Ann Dumoulin · Zedelgem, BE

Key dates

• Filing date: Jun 27, 1995
• Grant date: Sep 17, 1996
• Expiry date: Jun 27, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H05K2203/072
• WIPO field: Audio-visual technology
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing multichip modules having layer sequences made of dielectric material with conducting tracks embedded therein is characterized by the following features: (1) a temperature-resistant, base-resistant polymer having a dielectric constant .ltoreq.3 is used as a dielectric material, which is applied to a non-conductive substrate and serves as an edge boundary for currentless, autocatalytic build-up of the conducting tracks; (2) the dielectric material is provided with a layer made of material which is soluble in organic solvents (lift-off layer); (3) the dielectric material and the lift-off layer are structured in a single lithographic step, either a direct or an indirect structuring taking place and grooves having an aspect ratio .gtoreq.1 being formed in the dielectric material; (4) a metallic seed layer is applied to the dielectric material or rather to the lift-off layer through vapor deposition in a directed manner; (5) the lift-off layer is removed using an organic solvent; and (6) conducting tracks are created in the grooves through currentless metal deposition.