Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance
US5559055A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1994 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Dec 21, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The RC time constant of a semiconductor device is reduced by decreasing the capacitance C. The decrease in capacitance is achieved by replacing the interlayer silicon dioxide (dielectric constant of 4.0) with air (dielectric constant of 1.0). Alternatively, the air space can also be filled with another low dielectric constant material, such as an organic material having a dielectric constant in the range of about 2.2 to 3.4. In either case, the final effective dielectric constant of the device is lowered. As a result of lowering the effective dielectric constant, a smaller RC time constant is achieved, which results in higher device speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.