Method of fabricating an isolation trench for analog bipolar devices in harsh environments
US5561073A · kind A · utility
Inventors
Key dates
| Filing date | Apr 12, 1994 |
| Grant date | Oct 1, 1996 |
| Priority date | — |
| Expiry date | Apr 12, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/645
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention teaches a method of making an isolation trench. First, a silicon on insulator ("SOI") structure is provided having a conductive layer superjacent the insulator of the SOI. Second, a trench is formed down to the insulator of the SOI, thereby creating a first and second conductive region. Third, a first silicon dioxide layer is formed conformally with the sidewalls of the first and second conductive region. Fourth, a second silicon dioxide layer is formed conformally and superjacent the first silicon dioxide layer. Fifth, the remaining areas unfilled in the trench are filled with an undoped polysilicon filling. Sixth, the polysilicon layer is planarized. Seventh, an oxide cap is formed on top of the polysilicon refill. Eight, an isolation mask is formed, and the active area openings within the structure are etched down to the single crystal silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.