Memory array cell reading circuit with extra current branch
US5563826A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1995 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Apr 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read circuit comprises at least one array branch connected to at least one bit line, and a reference branch connected to a reference line. The array and reference branches each comprise a precharge circuit and load interposed between the supply and the bit line and reference line respectively. The reference load is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line. The reference line is connected to an extra-current transistor which is only turned on during equalization so that, during equalization, the selected bit line is supplied with a high current approximating that supplied to the reference line. As such, if the cell to be read is written, the output voltage of the array branch is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.