Surface counter doped N-LDD for high carrier reliability
US5565700A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1995 |
| Grant date | Oct 15, 1996 |
| Priority date | — |
| Expiry date | Apr 20, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/605
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new surface counter-doped lightly doped source and drain integrated circuit field effect transistor device is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.