System and method for obtaining correct byte addresses by using logical operations on 2 least significant bits of byte address to facilitate compatibility between computer architectures having different memory orders
US5572713A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1995 |
| Grant date | Nov 5, 1996 |
| Priority date | — |
| Expiry date | Jan 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer program-product for converting a program designed to be executed on a computer system employing a first predefined memory order, such as the Big Endian architecture, to a program which is executable on a computer system employing a second predefined memory order, such as the Little Endian architecture. The method and computer program-product uses the fact that performing a logical operation on the lower two bits of a byte address in one architecture converts that byte address to the equivalent byte address in the other architecture. The method and computer program-product are implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and operating on the two least significant bits of the byte address with a logical operation to generate two complementary bits used to replace the two least significant bits of the byte address to generate a new byte address that corresponds with the other architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.