Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology
US5573965A · kind A · utility
80Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1993 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Dec 17, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The base layer of high quality spacers, such as those used on the sidewalls of the gate stack of submicron devices (e.g., MOSFETs, EPROMs), are formed as composite, multi-layered structures of silicon oxides or of silicon oxides and silicon nitride.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.