Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits
US5576557A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Apr 14, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.