Electrically programmable and erasable memory device with depression in lightly-doped source
US5576569A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Apr 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
An improved structure and process of fabricating a programmable and erasable read only memory device wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide region is removed forming a depression in the surface. Impurity ions are implanted into the depression forming a lightly doped source region. A tunnel oxide layer is formed on the substrate surface. Next, the floating gate layer is formed on the tunnel oxide layer which at least partially overlies the lightly doped source region. A gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact opening are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and gate elements to form an electrical programmable memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.