Vertical power MOSFET and process of fabricating the same
US5578508A · kind A · utility
85Cited by
9References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1995 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Apr 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.