Power level detection circuit
US5581206A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1995 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | Jul 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output. The amplified comparator output functions to hold the system elements in a reset state at very low supply voltages and the one shot output functions to reset the system elements onc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.