Method for producing electroless barrier layer and solder bump on chip
US5583073A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1995 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Jan 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The present method for producing a barrier layer and a solder bump on a chip includes: a) providing a silicon chip with a bump base; b) forming a metal pad, e.g. an aluminum pad, on the bump base; c) having the metal pad contact with a solution containing about 120.about.150 g/l NaOH, 20.about.25 g/l ZnO, 1 g/l NaNO.sub.3 and 45.about.55 g/l C.sub.4 H.sub.4 KNaO.sub.6 .multidot.4H.sub.2 O to form thereon a zinc layer, and preferably further containing tartaric acid for reducing a dissolving rate of the metal pad.; d) having the zinc layer contact with a deposition solution to deposit thereon an electroless barrier layer, e.g. an electroless Ni-P layer; and e) dipping the resulting silicon chip into a molten solder bath to form a solder bump on the electroless barrier layer. The present invention is a simple process for manufacturing an electroless Ni-P and a solder bump on a chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.