Sequencer for a time multiplexed programmable logic device
US5583450A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1995 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Aug 18, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) includes at least one configurable element, a plurality of programmable logic elements for configuring the configurable element(s), and a sequencer coupled to the plurality of programmable logic elements. Each programmable logic element typically includes a plurality of memory cells, wherein the sequencer accesses one of the plurality of memory cells during one step in a sequence of steps, each step initiated by one or more trigger signals. If the sequencer receives a plurality of trigger signals simultaneously, then the sequencer prioritizes these signals. Generally, each step provides one configuration of the PLD. In one embodiment, the sequence of steps includes less than all configurations of the PLD. In another embodiment, one trigger signal initiates a plurality of sequences of configurations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.