Robert Anders Johnson
15Patents
13h-index
8Co-inventors
63Inventor score
Filing activity: Aug 18, 1995 → Jun 6, 2001
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5646545A | Time multiplexed programmable logic device | Electricity | 377 | Expired |
| US6091263A | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM | Electricity | 318 | Expired |
| US6480954B2 | Method of time multiplexing a programmable logic device | Electricity | 266 | Expired |
| US5629637A | Method of time multiplexing a programmable logic device | Electricity | 199 | Expired |
| US5600263A | Configuration modes for a time multiplexed programmable logic device | Physics | 195 | Expired |
| US5778439A | Programmable logic device with hierarchical confiquration and state storage | Electricity | 192 | Expired |
| US6150839A | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM | Electricity | 167 | Expired |
| US5583450A | Sequencer for a time multiplexed programmable logic device | Electricity | 162 | Expired |
| US5978260A | Method of time multiplexing a programmable logic device | Electricity | 152 | Expired |
| US5959881A | Programmable logic device including configuration data or user data memory slices | Electricity | 87 | Expired |
| US6263430A | Method of time multiplexing a programmable logic device | Electricity | 84 | Expired |
| US5784313A | Programmable logic device including configuration data or user data memory slices | Electricity | 49 | Expired |
| US5933369A | RAM with synchronous write port using dynamic latches | Physics | 15 | Expired |
| US6078528A | Delay control circuit using dynamic latches | Physics | 8 | Expired |
| US5920223A | Method and apparatus to improve immunity to common-mode noise | Electricity | 6 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.