Optimized binary adder for concurrently generating effective and intermediate addresses
US5583806A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1995 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Mar 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Carry-save adder techniques are used to concurrently generate Effective and Intermediate (also known as Relocation or Linear) Addresses with only a single carry propagation for each Address. Base, Scaled Index, and Displacement components are input to a first carry-save adder, which is common to both address calculations. A first sum vector and a first left-shifted carry vector are inputs to a first carry-propagate adder for generating the Effective Address. A second carry-save adder has as inputs a Segment Base Address, said first sum vector, and said first left-shifted carry vector. A second sum vector and a second left-shifted carry vector are inputs to a second carry-propagate adder for generating the Intermediate Address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.