Larry Widigen
20Patents
12h-index
6Co-inventors
66Inventor score
Filing activity: Aug 25, 1993 → Nov 16, 2001
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5454117A | Configurable branch prediction for a processor performing speculative execution | Physics | 145 | Expired |
| US5623614A | Branch prediction cache with multiple entries for returns having multiple callers | Physics | 58 | Expired |
| US5418736A | Optimized binary adders and comparators for inputs having different widths | Physics | 28 | Expired |
| US5802339A | Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit | Physics | 27 | Expired |
| US5923579A | Optimized binary adder and comparator having an implicit constant for an input | Physics | 25 | Expired |
| US5394351A | Optimized binary adder and comparator having an implicit constant for an input | Physics | 23 | Expired |
| US6671798B1 | Configurable branch prediction for a processor performing speculative execution | Physics | 21 | Expired |
| US6282639A | Configurable branch prediction for a processor performing speculative execution | Physics | 18 | Expired |
| US5919256A | Operand cache addressed by the instruction address for reducing latency of read instruction | Physics | 17 | Expired |
| US6041396A | Segment descriptor cache addressed by part of the physical address of the desired descriptor | Physics | 16 | Expired |
| US5590351A | Superscalar execution unit for sequential instruction pointer updates and segment limit checks | Physics | 16 | Expired |
| US5583806A | Optimized binary adder for concurrently generating effective and intermediate addresses | Physics | 16 | Expired |
| US5815699A | Configurable branch prediction for a processor performing speculative execution | Physics | 12 | Expired |
| US6108777A | Configurable branch prediction for a processor performing speculative execution | Physics | 11 | Expired |
| US5517440A | Optimized binary adders and comparators for inputs having different widths | Physics | 10 | Expired |
| US5675758A | Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations | Physics | 8 | Expired |
| US5822786A | Apparatus and method for determining if an operand lies within an expand up or expand down segment | Physics | 6 | Expired |
| US5699279A | Optimized binary adders and comparators for inputs having different widths | Physics | 4 | Expired |
| US6360318B1 | Configurable branch prediction for a processor performing speculative execution | Physics | 1 | Expired |
| US6195745A | Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.