Testing hot carrier induced degradation to fall and rise time of CMOS inverter circuits
US5587665A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 1995 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Jul 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Performance degradation resulting from hot carrier stress is determined using a special test circuit. The test circuit is formed using a string of inverters on an integrated circuit. The string of inverters is connected in series. Every other inverter in the string of inverters uses cascaded transistors so that performance of the inverters with cascaded are not degraded by introduced hot carrier stress. For example, odd numbered inverters are each constructed using cascaded PMOSFETs and cascaded NMOSFETs and even numbered inverters are each constructed using a single PMOSFET and a single NMOSFET. On an input of the string of inverters, a first signal is placed which transitions from logic 0 to logic 1. Propagation delay of the first signal through the string of inverters is measured. Also, a second signal which transitions from logic 1 to logic 0 is placed on the input of the string of inverters. Propagation delay of the second signal through the string of inverters is measured. Then, sufficient hot carrier stress is added to the string of inverters so that inverters not constructed using cascaded transistors will have degraded performance. After introduction of the hot carrier str…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.