Single chamber CVD process for thin film transistors
US5589233A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/905
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of depositing layers of intrinsic amorphous silicon and doped amorphous silicon sequentially on a substrate in the same CVD chamber without incurring a dopant contamination problem. The method can be carried out by first depositing an additional layer of a dielectric insulating material prior to the deposition process of the intrinsic amorphous silicon layer. The additional layer of insulating material deposited on the substrate should have a thickness such that residual insulating material coated on the chamber walls is sufficient to cover the residual dopants on the chamber walls left by the deposition process of the previous substrate. This provides a clean environment for the next deposition process of an intrinsic amorphous silicon layer on a substrate in the same CVD chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.