Superscalar execution unit for sequential instruction pointer updates and segment limit checks
US5590351A · kind A · utility
16Cited by
22References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1994 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Jan 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the execution unit includes Next EIP (Extended Instruction Pointer) selection logic, Current EIP selection logic, an EIP History RAM, a Dual EIP Adder, a CS Limit check adder, limit checking combinational logic, and a limit fault History RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.